A considerable portion of portable electronic devices, such as cellular telephones, include memory devices. Therefore, a goal in the semiconductor and electronics industry is to make memory devices in portable electronic devices, smaller and more power efficient. For example, a challenge is to support trends to smaller sized memory devices, such as the industry trend from “65 nm” technology to “45 nm” technology. Since portable electronic devices rely almost exclusively on battery power, components such as memory devices should be power efficient, minimizing power consumption and power dissipation.
Semiconductor memories or memory devices can be characterized as volatile random access memories (RAMs) or nonvolatile read only memories (ROMs), where RAMs can include static RAM (SRAM) and dynamic RAM (DRAM). In general, SRAM and DRAM differ in the way they store a state of a bit in a bit cell of the memory. In SRAM, each bit cell can include circuitry (typically a transistor circuit) that implements a bi-stable latch. Such a transistor circuit can rely on transistor gain and positive feedback, where one of two possible states are assumed, i.e., “ON” or state 1, or “OFF” or state 2. An application of voltage to the bi-stable latch induces the state to change from one to the other. This allows a state written to a bit cell to be retained until the bit cell is reprogrammed.
An SRAM may be arranged as a matrix or array of memory cells or bit cells fabricated in an integrated circuit (IC) chip, where address decoding in the IC chip allows access to each bit cell for read/write functions. SRAM bit cells can include active feedback from cross-coupled inverters in the form of a latch to store or “latch” a bit of information. These SRAM bit cells can be arranged in rows, such that blocks of data (e.g., words, bytes, etc.) can be written or read simultaneously.
A particular challenge in memory device technology in general, and SRAM in specific, is variability in process and manufacture of memory devices. For example, there can be significant variances in the bit cells of SRAM devices that affect performance. The variances may further be complicated due to actual operating temperature changes.